\documentclass{article}

\usepackage[top=25mm,bottom=25mm,left=25mm,right=25mm]{geometry}
\usepackage{graphicx}
\usepackage{amsmath}
\usepackage{subfig}
\usepackage{maplestd2e}
\usepackage{epstopdf}
\usepackage[framed,autolinebreaks,useliterate]{mcode}
\usepackage{subfig}
\setlength{\parindent}{0pt}
\begin{document}

\title{ESP project - System level design of Sigma-Delta converter}
\author{Floris van Nee \& Simon Dirlik}

\maketitle

\section{} %1
Using fractional expansion, we can write the transfer function like this:
\[
H(z) = \frac{2} {z-1} + \frac{1} {(z-1)^2} 
\]
So the gain $A$, as shown in the figure is 2 for the first integrator and 1 for the second integrator.

\section{} %2
A general advantage of the RC integrator is that it can deal with large signals, a disadvantage is that it does not work well with high frequencies. With the gm-C integrator this is reversed, it works well at high frequencies, but with smaller signals, \textasciitilde1Vpp. We choose to implement the RC integrator, because the signals in our filter will be larger than that and the bandwidth, although high, is not too high for a RC implementation. Because the RC implementation uses a feedback loop, non-linearities will not have as much effect on the output as it will have in the gm-C implementation. These non-linearities are a much bigger problem in the gm-C topology, as the CMOS inverter which is used later in the exercise to replace the ideal gm is greatly non-linear.\\\\
The values for the RC components are calculated as follows:\\
From analog lab 4 we got a sampling frequency of 800MHz. Transforming the transfer function to the s-domain with a approximation of $e^{st} = 1 + st$, the following is obtained:

\[
\frac{2(st + 0.5)}{st^2}
\]

Thus, $s$ is given as: $-0.5 \cdot 800 \cdot 10^6 = -400 \cdot 10^6$. With this, the values of R and C can be calculated.

The time constant in an RC filter is $RC$, so $RC=\frac{1}{400\cdot10^6}$. The following values will fit nicely in this equation $R=10k\Omega$, $C=0.25$pF. Each integrator consists of two resistor, their ratio is the gain. One of the integrators has a gain of 1, so the resistors in this integrator will be equal. The other has a gain of 2, so we adjust the secondary resistor to $2\cdot10k=20k\Omega$ and the capacitor to $\frac{0.25}{2}=0.125$pF. We will use these values as starting points, later on they will change.

\section{} %3
Figure \ref{fig:ex3_scheme} shows the resulting circuit, figure \ref{fig:ex3_int_outs} shows the outputs of the first and second integrator and figure \ref{fig:ex3_out} shows the final output.
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex3_scheme.png}
		\caption{Scheme of the ADC using ideal components.}
		\label{fig:ex3_scheme}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex3_int_outs.png}
		\caption{Outputs of the first (green) and second (blue) integrator.}
		\label{fig:ex3_int_outs}
	\end{center}
\end{figure}
\clearpage
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex3_out.png}
		\caption{Final output of the ADC.}
		\label{fig:ex3_out}
	\end{center}
\end{figure}
\section{} %4
Writing the transfer function from output of the comparator to input of the comparator, we can determine which values can safely be changed. This transfer function can be written as:

\[
\frac{-1}{sR_3C_2} \cdot \frac{-v_o}{sR_1C_1} + \frac{v_o}{sR_4C_2} = \frac{v_o}{s^2R_1R_3C_1C_2} + \frac{v_o}{sR_4C_2} = v_o \cdot \frac{R_4 + sR_1R_3C_1}{s^2R_1R_3R_4C_1C_2}
\]

It can be seen that in order to keep the same zero in the transfer function, the ratio between the resistors 1 to 3 and the capacitor $C_1$ should remain the same. The capacitor $C_2$ can be changed freely.

We changed the values to:
\[\begin{split}
	R1	&= 10k\Omega\\
	R2	&= 10k\Omega\\
	C1	&= 1pF\\
	R3	&= 5k\Omega\\
	R4	&= 10k\Omega\\
	C2	&= 0.3pF\\
\end{split}\]
Figure \ref{fig:ex4_int_outs} shows the outputs of the first and second integrator and figure \ref{fig:ex4_out} shows the final output.
\clearpage
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex4_int_outs.png}
		\caption{Outputs of the first (green) and second (blue) integrator using adjusted values for the R's and C's.}
		\label{fig:ex4_int_outs}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex4_out.png}
		\caption{Final output of the ADC using adjusted values for the R's and C's.}
		\label{fig:ex4_out}
	\end{center}
\end{figure}

\section{} %5
The results are shown in figure \ref{fig:ex5}. The output of CMOS inverter using the given values gives $V_{out}=1.35$, this needs to be lower. A smaller W/L ratio gives lower output current and thus voltage, so we decided to increase the length of the PMOS. After some trial and error we found the values in figure \ref{fig:ex5_inverter}. The difference in ratio's between PMOS and NMOS can be explained by looking at the beta ratio effect. We have approximated the right values for the W/L ratio's so $\beta_n\approx\beta_p$:
\[\begin{split}
	\beta_n									& \approx \beta_p\\
	k_n\cdot\left(\frac{W_n}{L_n}\right)	& \approx k_p\cdot\left(\frac{W_p}{L_p}\right)\\
	k_n\cdot\left(\frac{0.5}{1.5}\right)	& \approx k_p\cdot\left(\frac{0.5}{0.33}\right)\\
	k_n										& \approx 4.5\cdot k_p\\
\end{split}\]
So the difference in W/L ratio's is because of the difference in $k$'s.

\begin{figure}[ht]
	\begin{center}
		\subfloat[Results from DC operating point.]{\label{fig:ex5_op}\includegraphics[scale=0.7]{ex5_op.png}}
		\subfloat[CMOS inverter.]{\label{fig:ex5_inverter}\includegraphics[scale=0.5]{ex5_inverter.png}}
		\caption{}
		\label{fig:ex5}
	\end{center}
\end{figure}

\section{} %6
The result is shown in figure \ref{fig:ex6_freq}, the gain at low frequencies is limited by $V_{DD}$, which is set to $1.8V$.
This works sufficiently as an integrator because the transfer function of an integrator is $H = \frac{1}{sRC}$, which means is has a linear slope. Figure \ref{fig:ex6_freq} shows that the output is indeed linear between $5MHz$ and $10GHz$, which covers the region in which our integrator needs to operate. The phase of this transfer function (a linear transfer function) should be constant at $90^\circ$. By looking at the figure we see that the phase is not exactly constant, however, the change between $100MHz$ and $1GHz$ is about $5^\circ$ around $90^\circ$, which suffices.
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex6_freq.png}
		\caption{Plot of gm-C integrator.}
		\label{fig:ex6_freq}
	\end{center}
\end{figure}
\section{} %7
The gain of the inverter is given by:
\[\begin{split}
	A		& = gm\cdot(R_o // Z_C)\\
			& = gm\cdot(\dfrac {R_o\cdot Z_C} {R_o + Z_C})\\
	Z_C		& = \frac{1}{2\pi fC}\\
\end{split}\]
In the 1/f region the slope is linear, so we can pick two values for $f$ and read their corresponding gains. This leaves only two unknowns and two equations. From LTspice we see that the gain is $-28.6+915mdB=-27.685dB$ at $400MHz$ and $-8.7dB+915mdB=-7.785dB$ at $40MHz$. Now we can use maple to solve these equations:
\input{ex7_gmxrout} 
\section{} %8
The result is shown in figure \ref{fig:ex8_freq}. The plot shows that the slope is no longer linear, it has a curve and is constant in the region around $800MHz$, so it is no longer suitable as an integrator.
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex8_freq.png}
		\caption{Plot of incorrect RC integrator.}
		\label{fig:ex8_freq}
	\end{center}
\end{figure}
\section{} %9
The result is shown in figure \ref{fig:ex9_freq1}. This does not function as an integrator, the curve is almost gone, the phase however is far from a constant $90^\circ$. This is because the length of the nmos transistor is so large that its parasitic capacitances interfere. To correct for this we have to decrease the size of the nmos and we will add a zero to the transfer function by putting a resistor with value $\frac{1}{gm}$ in series with the $1pF$ capacitance. Measurements in LTspice show that gm is about $24mS$, so the resistor should be about $40\Omega$. The resulting scheme is shown in figure \ref{fig:ex9_inverter} and its result is shown in figure \ref{fig:ex9_freq2}, this figure also shows that the gain at low frequencies is a little bigger as a result of the changes.
\section{BONUS QUESTION} %10
The rise and fall delays of the inverter depend on the widths of PMOS and NMOS, increasing the widths gives shorter delays. At high frequencies the delays were apparently too large making the system instable. By increasing the widths this problem is solved. Theoretically, the best results are obtained when the width of PMOS is a little over twice as large as the width of the NMOS in our inverter the PMOS is a little over four times as wide as the NMOS.
\clearpage
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex9_freq1.png}
		\caption{Plot of incorrect RC integrator with increased transistor widths.}
		\label{fig:ex9_freq1}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[scale=0.4]{ex9_inverter.png}
		\caption{Scheme of correct RC integrator with changed transistor and series resistor.}
		\label{fig:ex9_inverter}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex9_freq2.png}
		\caption{Plot of correct RC integrator with changed transistor and series resistor.}
		\label{fig:ex9_freq2}
	\end{center}
\end{figure}
\section{} %11
Figure \ref{fig:ex11_R40freq} shows the result after changing the values of the components to what was found in exercise 4, it is almost the same as figure \ref{fig:ex9_freq2} and it will do, however conducting the same measurements for gm as in exercise shows that a $50\Omega$ resistor should work better with a $0.25$pF capacitor. This result is shown in figure \ref{fig:ex11_R50freq}.
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex11_R40freq.png}
		\caption{Plot integrator with correct component values and $40\Omega$ series resistor.}
		\label{fig:ex11_R40freq}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex11_R50freq.png}
		\caption{Plot integrator with correct component values and $50\Omega$ series resistor.}
		\label{fig:ex11_R50freq}
	\end{center}
\end{figure}
\section{} %12
Figure \ref{fig:ex12_scheme} shows the resulting circuit using real components, figure \ref{fig:ex12_int_outs} shows the outputs of the first and second integrator and figure \ref{fig:ex12_out} shows the final output. We did not need to change the values of the components anymore to get satisfying results.
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex12_scheme.png}
		\caption{Scheme of the ADC using real components.}
		\label{fig:ex12_scheme}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex12_int_outs.png}
		\caption{Outputs of the first (green) and second (blue) integrator using real components.}
		\label{fig:ex12_int_outs}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{ex12_out.png}
		\caption{Final output of the ADC with real components.}
		\label{fig:ex12_out}
	\end{center}
\end{figure}
\clearpage

\section{} %13
Figure \ref{fig:sinad30db} shows the result from the Matlab spectral analysis. A SINAD of 30 dB was obtained. The time domain output can be found in figure \ref{fig:ex12_int_outs} and \ref{fig:ex12_out}. There are some important differences with the Simulink results. First, it can be seen that the noise shaping behaving is far from optimal. After 100 MHz, the shaping goes down again. At low frequencies there is not much noise, though there is a lot of harmonic distortion, both even and odd. This is different from the Simulink simulations, as here only odd harmonic distortion was present.

The time domain output also shows differences with the Simulink simulation. The frequency at which the signal goes from high to low and back is less than in the Simulink simulation. This is caused by propagation delays in the comparator. Also, when looking at the difference between the simulation of the real components and of the ideal components, the output of the integrators is different. The output of the second integrator is too high and clips. Thus, here it does not have a high gain anymore and this causes bad performance. This also causes the virtual ground nodes to not have a voltage close to 0.9V anymore. Much time was spent trying to figure out how to improve this, but no suitable solution was found.

Power dissipation of the circuit per integrator can be computed as:

\[
P = 8kT \cdot f \cdot SNR \cdot \frac{V_B}{V_{pp}}
\]

With $V_B = 1.8$V and $V_{pp} = 1.4$ V, an SNR of 60 dB and a frequency of 800 MHz, this leads to a minimum power dissipation of 2.04 nW per integrator. The circuit has two integrators, so this is 4.08 nW, not taking into account the sampling comparator. However, the actual power dissipation is much larger, because this only calculates the minimum for an ideal integrator. Since our integrator consists of a CMOS device where both NMOS and PMOS are turned on most of the time, there is a lot of power dissipation there. However, we were not able to find formulas to calculate the exact power dissipation.

\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{sinad30db.eps}
		\caption{}
		\label{fig:sinad30db}
	\end{center}
\end{figure}
\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{sinad33db_old_values.eps}
		\caption{}
		\label{fig:sinad33db_old_values}
	\end{center}
\end{figure}

\section{} %14
First, we tried to optimize the values of the R and C to obtain large swings at the input of the comparator. However, at first this did not really lead to better performance. This also had to do with the fact that the output of the second integrator was already clipping. Since we had not been able to fix that, we tried something different. All resistors were scaled down and capacitors as well. The resulting schematic can be found in figure \ref{fig:optimal_real}. The spectral analysis of the simulation results can be found in figure \ref{fig:sinad33db_old_values}. With this, a SINAD of 33 dB was obtained.

Comparing these spectral results with the results of the previous exercise, it can be seen that the THD is less here. The noise shaping behavior is a bit worse, however the harmonic distortions have a much smaller peak. There are still even and odd distortions though. Overall, this leads to a 3 dB better SINAD.

\begin{figure}[ht]
	\begin{center}
		\includegraphics[width=\textwidth]{optimal_real.png}
		\caption{}
		\label{fig:optimal_real}
	\end{center}
\end{figure}

\end{document}
